For who? Students , assistants / junior researchers , engineers and scientists interested in the development of electronic embedded systems to reconfigurable FPGA platforms with explanations of basic steps and slow start using E2LP educational platform

Workshop discription
This workshop will introduce participants to the E2LP platform,  demonstrate its application, and allow participants to try to design electronic circuits on this platform. In addition, as part of the project, a Lab system for remote operation of the platform at a distance was developed and will also be demonstrated on the workshop.

Total number of participants is limited to 16 and the seats must be reserved. 

Lecturers:
Dr. sc. Peter Škoda, Ruđer Bošković Institute, Division of electronics
Mag. ing. el. Ivan Sović, Ruđer Bošković Institute, Centre for informatics and computing (CIR)

When?  Wednesday 15.07.2015. at 13:00

Where?  RBI, Library, V. Wing

Reservation:

Prior Computer Architecture Education based on the E2LP implementation

CRAY Reincarnation on E2LP platforme

Present day development of the FPGAs enables us to go much further than only implementing reasonably simple Memory Algorithm Processors of, it enables us to implement even very complex computer architectural designs of the past and to enable prospective electronic engineers and computer designers and constructors, as well as computer scientists, to experiment with those architectures, to gain experience and primarily to open up new possible perspectives on future computer architecture designs by having deep experience with the sometimes completely forgotten major ideas and implementations. The present moment of computer development obviously shows a huge lack of basic architectural work, though we are all aware of the quite strongly felt limits of present day high-end computer principles, not only in both power consumption and speed restrictions, but probably mostly in the complexity of coordination (system and algorithm), and primarily in the effectiveness of the cycle between a human idea and finalised computer processing, that is the overall Productivity of the human-computer interaction is quite low.

Many Advanced Excercises can be made with the core Cray processor implementation on the E2LP board. The expansion of a Cray-1 design into a Cray-XMP, Cray-2 or some other computer from that series enables deep insight in the correspondence of instruction sets, registers and interdependent timings. Connecting the board's DRAM to the core Cray processor enables the student to study the possibilities of banking, and the problems involved in coordination of the access times, asynchronicity and internal chaining and pipelining. Adapting the instruction set, implementing IEEE floating point, re-arrangeing of the register sets and their access principles etc. are extremely important exercises to those who intend to work in processor design and construction, be it from the hardware, be it from the software side. Downscaling the Cray processor to e.g. 32-bits may show merits for special applications. As the data highways in the Cray processor are all 64-bit, and have to connect, inter alias, every vector register unit with every vector functional unit, the memory functional unit and with the floating point functional units, plus all the coordination busses, a downgrading to 32 bits would produce a significantly smaller processor, giving much additional space on the E2LP FPGA

An important aspect for the usefulness of the Cray processors for teaching purposes is that the documentation of the Cray designs preserved (by Bitsavers.org) is very thorough and extensive, therefore a full understanding and implementation is possible. Cray processors are completely hardwired (i.e. not microcoded) and fully synchronous, and therefore an excellent example of efficacy and the complexity/performance tradeoffs of computer design.

Video: Embedded Computer Engineering Learning Platform (E2LP) - FP7 Project