Za koga? Studente, asistente/znanstvene novake, inženjere i znanstvenike zainteresirane za razvoj elektroničkih ugradbenih sustava na rekonfigurabilnim FPGA platformama uz pojašnjenja osnovnih koraka i laganog starta pomoću E2LP edukativne platforme

Opis radionice
Stjecanje vještina iz elektroničkog i računalnog inženjerstva povlači nužno iskustvo sa širokim spektrom state-of-the-art tehnologija. Upoznavanje studenata s ovim tehnologijama uvijek ima isti konačni cilj - naučiti koristiti komponente u svrhu rješavanja dobro definiranog inženjerskog problema. No, dodatno opterećenje koje je potrebno za privikavanje na nove hardverske platforme može biti poveće, a cijeli postupak edukacije neefikasan.

U cilju smanjenja krivulje učenja razvoja elektroničkih sustava, E2LP EU-FP7 projekt razvio je unificiranu platformu dostatnu za cjelokupnu edukaciju novih inženjera, što ne uključuje samo hardverske komponente, već i start-up kit sa svim specifikacijama, detaljima, predloženim kurikulumima i razrađenim laboratorijskim vježbama. Moguće primjene platforme nisu ograničene samo na nastavu, te ona ima svoje mjesto i u razvoju digitalnih elektroničkih i ugrađenih računalnih sustava temeljenih na FPGA ili mikrokontrolerskim komponentama.

Ova radionica upoznati će polaznike s E2LP platformom, demonstrirati njenu primjenu, te omogućiti polaznicima da svojim rukama isprobaju dizajn elektroničkih sklopova na ovoj platformi. Osim toga, u sklopu projekta razvijen je i Remote Lab sustav za rad s platformom na daljinu koji će biti demonstiran u sklopu radionice.

Broj polaznika na radionici ograničen je na 16 osoba, a mjesta će biti popunjavana po redoslijedu prijave.

Teme radionice
- Uvod u E2LP projekt
- Upoznavanje s E2LP FPGA hardverskom platformom
- Demo E2LP platforme
- Hands-on s platformom, povezivanje s računalom i upoznavanje s razvojnim alatima
- Implementacija jednostavnog hardverskog dizajna i pokretanje na E2LP ploči
- Demonstracija Remote Lab funkcionalnosti
- Detaljne informacije o start-up kitu i gdje pronaći dodatne informacije

Predavači radionice:
Dr. sc. Peter Škoda, Institut Ruđer Bošković, Zavod za elektroniku (ZEL)
Mag. ing. el. Ivan Sović, Institut Ruđer Bošković, Centar za informatiku i računarstvo (CIR)

Kada?  Srijeda 15.07.2015. u 13h

Gdje?  IRB, knjižnica V. krila

Prijave:

Prior Computer Architecture Education based on the E2LP implementation

CRAY Reincarnation on E2LP platforme

Present day development of the FPGAs enables us to go much further than only implementing reasonably simple Memory Algorithm Processors of, it enables us to implement even very complex computer architectural designs of the past and to enable prospective electronic engineers and computer designers and constructors, as well as computer scientists, to experiment with those architectures, to gain experience and primarily to open up new possible perspectives on future computer architecture designs by having deep experience with the sometimes completely forgotten major ideas and implementations. The present moment of computer development obviously shows a huge lack of basic architectural work, though we are all aware of the quite strongly felt limits of present day high-end computer principles, not only in both power consumption and speed restrictions, but probably mostly in the complexity of coordination (system and algorithm), and primarily in the effectiveness of the cycle between a human idea and finalised computer processing, that is the overall Productivity of the human-computer interaction is quite low.

Many Advanced Excercises can be made with the core Cray processor implementation on the E2LP board. The expansion of a Cray-1 design into a Cray-XMP, Cray-2 or some other computer from that series enables deep insight in the correspondence of instruction sets, registers and interdependent timings. Connecting the board's DRAM to the core Cray processor enables the student to study the possibilities of banking, and the problems involved in coordination of the access times, asynchronicity and internal chaining and pipelining. Adapting the instruction set, implementing IEEE floating point, re-arrangeing of the register sets and their access principles etc. are extremely important exercises to those who intend to work in processor design and construction, be it from the hardware, be it from the software side. Downscaling the Cray processor to e.g. 32-bits may show merits for special applications. As the data highways in the Cray processor are all 64-bit, and have to connect, inter alias, every vector register unit with every vector functional unit, the memory functional unit and with the floating point functional units, plus all the coordination busses, a downgrading to 32 bits would produce a significantly smaller processor, giving much additional space on the E2LP FPGA.

An important aspect for the usefulness of the Cray processors for teaching purposes is that the documentation of the Cray designs preserved (by Bitsavers.org) is very thorough and extensive, therefore a full understanding and implementation is possible. Cray processors are completely hardwired (i.e. not microcoded) and fully synchronous, and therefore an excellent example of efficacy and the complexity/performance tradeoffs of computer design.

Video: Embedded Computer Engineering Learning Platform (E2LP) - FP7 Project